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• 3358706760 Add compare instructions master Denis Tereshkin 2025-12-06 11:52:11 +0700
• 153af7c108 Add flag instructions Denis Tereshkin 2025-12-03 20:29:14 +0700
• 8a1f41bfa8 Add shift/rotate operations Denis Tereshkin 2025-12-01 18:25:23 +0700
• 5859c1d703 Add memory INC/DEC Denis Tereshkin 2025-11-30 10:51:15 +0700
• 0f1ab8fd19 Add STX, STY instructions Denis Tereshkin 2025-11-08 20:53:57 +0700
• 978d21b4ab Fix verification for branches/jmp Denis Tereshkin 2025-11-08 20:38:23 +0700
• e66e89bbd9 Fix timings for STA Denis Tereshkin 2025-11-08 19:04:11 +0700
• 63d9b4cf2a Add postindexed address mode Denis Tereshkin 2025-11-08 13:15:21 +0700
• bed4bc7316 Add preindexed indirect mode Denis Tereshkin 2025-11-07 17:14:57 +0700
• 2c5e25416b Add indexed zp addr mode Denis Tereshkin 2025-11-07 09:19:32 +0700
• 69162741e2 Add DEY instruction Denis Tereshkin 2025-11-06 19:57:13 +0700
• 494ee94d20 Add ZP address mode Denis Tereshkin 2025-11-06 19:24:57 +0700
• f88a2c3bdb Verify implemented instructions Denis Tereshkin 2025-11-06 17:50:04 +0700
• cc9a2e0dc4 Implement some of instructions Denis Tereshkin 2025-11-06 12:47:16 +0700
• 0dd5d0341a ALU,decoder: make combinatorial Denis Tereshkin 2025-10-28 23:12:13 +0700
• 064b1c0727 Add decoder Denis Tereshkin 2023-12-02 11:25:32 +0700
• 8ccea9566e Add ALU Denis Tereshkin 2023-11-23 22:26:50 +0700