asakul/slon
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Denis Tereshkin 4ea9ac7307 Add stack instructions
2025-12-22 11:02:43 +07:00
doc
Add ALU
2023-11-23 22:26:50 +07:00
src
Add stack instructions
2025-12-22 11:02:43 +07:00
tests
ALU,decoder: make combinatorial
2025-10-28 23:12:13 +07:00
Description
6502 implementation in SystemVerilog
1.7 MiB
Languages
SystemVerilog 100%