Add STX, STY instructions

src/cpu.verilog

@@ -528,18 +528,38 @@ always_comb
       mem_wr = 0;
       if (state == STATE_EXECUTE_DATA_2)
         begin
-            if(decoded_instr == I_STA)
+            if (decoded_instr == I_STA)
               begin
+                  mem_wr = 1'b1;
                   mem_data_wr = A;
+              end
+            else if (decoded_instr == I_STX)
+              begin
                   mem_wr = 1'b1;
+                  mem_data_wr = X;
+              end
+            else if (decoded_instr == I_STY)
+              begin
+                  mem_wr = 1'b1;
+                  mem_data_wr = Y;
               end
         end
       else if (state == STATE_EXECUTE_ZP)
         begin
             if(decoded_instr == I_STA)
               begin
+                  mem_wr = 1'b1;
                   mem_data_wr = A;
+              end
+            else if(decoded_instr == I_STX)
+              begin
                   mem_wr = 1'b1;
+                  mem_data_wr = X;
+              end
+            else if(decoded_instr == I_STY)
+              begin
+                  mem_wr = 1'b1;
+                  mem_data_wr = Y;
               end
         end
   end
@@ -693,6 +713,8 @@ begin
              decoded_instr == I_LDX ||
              decoded_instr == I_LDY ||
              decoded_instr == I_STA ||
+             decoded_instr == I_STX ||
+             decoded_instr == I_STY ||
              decoded_instr == I_AND ||
              decoded_instr == I_EOR ||
              decoded_instr == I_ORA ||
@@ -727,12 +749,26 @@ always @(posedge clk)
           assert(Y == $past(mem_data));
         else if (f_prev_instruction == I_STA)
           assert(A == $past(A));
+        else if (f_prev_instruction == I_STX)
+          assert(X == $past(X));
+        else if (f_prev_instruction == I_STY)
+          assert(Y == $past(Y));
 
         if (f_prev_instruction == I_STA)
           begin
               assert($past(mem_wr, 2) == 1'b1);
               assert($past(mem_data_wr, 2) == $past(A, 2));
           end
+        else if (f_prev_instruction == I_STX)
+          begin
+              assert($past(mem_wr, 2) == 1'b1);
+              assert($past(mem_data_wr, 2) == $past(X, 2));
+          end
+        else if (f_prev_instruction == I_STY)
+          begin
+              assert($past(mem_wr, 2) == 1'b1);
+              assert($past(mem_data_wr, 2) == $past(Y, 2));
+          end
         else
           begin
               assert($past(mem_wr, 2) == 1'b0);