slon/src/alu.verilog

module alu
  (
    input logic [7:0]  A,
    input logic [7:0]  B,
    input logic        C,
    input logic [2:0]  sel,
    output logic [7:0] result,
    output logic r_n,
    output logic r_z,
    output logic r_v,
    output logic r_c
   );

`include "parameters.vh"

    reg [8:0]   buffer;
    wire [8:0]  sum;
    wire [8:0]  diff;

assign r_z = result[7:0] == 0;
assign r_n = result[7];
assign sum = A + B + C;
assign diff = A - B - (1 - C);

always_comb
  begin
      case (sel)
        OP_OR:
          begin
              result = A | B;
              r_v = 0;
              r_c = 0;
          end
        OP_AND:
          begin
              result = A & B;
              r_v = 0;
              r_c = 0;
          end
        OP_EOR:
          begin
              result = A ^ B;
              r_v = 0;
              r_c = 0;
          end
        OP_ADC:
          begin
              result = sum[7:0];
              r_c = sum[8];
              r_v = !(A[7] ^ B[7]) & (A[7] ^ sum[7]);
          end
        OP_SUB:
          begin
              result = diff;
              r_c = diff[8];
              r_v = !(A[7] ^ B[7]) & (A[7] ^ diff[7]);
          end
        OP_ROT:
          begin
              if (B == SHIFT_LEFT) begin
                  result[7:1] = A[6:0];
                  result[0] = C;
                  r_c = A[7];
              end
              else begin
                  result[6:0] = A[7:1];
                  result[7] = C;
                  r_c = A[0];
              end
          end
        OP_SHF:
          begin
              if (B == SHIFT_LEFT) begin
                  result[7:1] = A[6:0];
                  result[0] = 0;
                  r_c = A[7];
              end
              else begin
                  result[6:0] = A[7:1];
                  result[7] = 0;
                  r_c = A[0];
              end
          end
      endcase // case sel
  end

endmodule