slon/src/alu.verilog

module alu
  (
   input        nrst,
   input        clk,
   input [7:0]  A,
   input [7:0]  B,
   input        C,
   input [2:0]  sel,
   output [7:0] result,
   output       r_n,
   output       r_z,
   output reg   r_v,
   output reg   r_c
   );

   wire        rst = !nrst;
   reg [8:0] buffer;
   wire [8:0] sum;
   wire [8:0] diff;

   assign result[7:0] = buffer[7:0];
   assign r_z = buffer[7:0] == 0;
   assign r_n = buffer[7];
   assign sum = A + B + C;
   assign diff = A - B - (1 - C);

   initial begin
      buffer <= 0;
      r_v <= 0;
      r_c <= 0;
   end

   always @(posedge clk)
     begin
        case (sel)
          OP_OR:
            begin
               buffer <= A | B;
            end
          OP_AND:
            begin
               buffer <= A & B;
            end
          OP_EOR:
            begin
               buffer <= A ^ B;
            end
          OP_ADC:
            begin
               buffer <= sum;
               r_c <= sum[8];
               r_v <= !(A[7] ^ B[7]) & (A[7] & sum[7]);
            end
          OP_SUB:
            begin
               buffer <= diff;
               r_c <= diff[8];
               r_v <= !(A[7] ^ B[7]) & (A[7] & diff[7]);
            end
          OP_ROT:
            begin
               if (B == SHIFT_LEFT) begin
                  buffer[8:1] <= A[7:0];
                  buffer[0] <= C;
                  r_c <= A[7];
                 end
               else begin
                  buffer[6:0] <= A[7:1];
                  buffer[7] <= C;
                  r_c <= A[0];
                end
            end
          OP_SHF:
            begin
               if (B == SHIFT_LEFT) begin
                  buffer[8:1] <= A[7:0];
                  buffer[0] <= 0;
                  r_c <= A[7];
                 end
               else begin
                  buffer[6:0] <= A[7:1];
                  buffer[7] <= 0;
                  r_c <= A[0];
                end
            end
        endcase // case sel
     end

endmodule