6502 implementation in SystemVerilog
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754 B

`default_nettype none
module dmux(sel, i_pc, i_a, i_x, i_y, i_sp, i_aux, o_mux);
input wire [2:0] sel;
input wire [15:0] i_pc;
input wire [7:0] i_a;
input wire [7:0] i_x;
input wire [7:0] i_y;
input wire [7:0] i_sp;
input wire [15:0] i_aux;
output logic [15:0] o_mux;
`include "parameters.vh"
always_comb
begin
o_mux = 0;
if (sel == DMUX_PC)
o_mux = i_pc;
else if (sel == DMUX_A)
o_mux[15:0] = { 8'h0, i_a };
else if (sel == DMUX_X)
o_mux[15:0] = { 8'h0, i_x };
else if (sel == DMUX_Y)
o_mux[15:0] = { 8'h0, i_y };
else if (sel == DMUX_SP)
o_mux[15:0] = { 8'h1, i_sp };
else if (sel == DMUX_AUX)
o_mux = i_aux;
end
endmodule