slon/tests/test_alu.verilog

module test_alu;
   initial begin
      $dumpfile("test.vcd");
      $dumpvars(0, test_alu);
   end

`define assert(signal, value) \
if (signal !== value) begin \
   $display("ASSERTION FAILED in %m: signal != value"); \
     $finish; \
       end


   reg nrst = 1;
   reg clk = 0;

   reg [7:0] A;
   reg [7:0] B;
   reg       C;
   reg [2:0] op_sel;

   wire [7:0] result;
   wire       r_z;
   wire       r_n;
   wire       r_c;
   wire       r_v;

   always #1 clk = !clk;

   alu my_alu(
              .nrst(nrst),
              .clk(clk),
              .A(A),
              .B(B),
              .C(C),
              .sel(op_sel),
              .result(result),
              .r_z(r_z),
              .r_n(r_n),
              .r_c(r_c),
              .r_v(r_v));

   initial begin
      #10 A = 8'h11;
      B = 8'h22;
      C = 0;
      op_sel = 0; // OR

      #2 `assert (result, 8'h33);

      #2 op_sel = 1; // AND

      #2 `assert (result, 8'h00);

      #2 op_sel = 2; // EOR

      #2 `assert (result, 8'h33);

      #2  A = 8'h22;
      B = 8'h22;

      #2 `assert (result, 8'h00);

      #2 op_sel = 3; // ADC

      #2  A = 8'h22;
      B = 8'h22;

      #2 `assert (result, 8'h44);

      #2 C = 1; // ADD with CARRY

      #2 `assert (result, 8'h45);

      #2  A = 8'hf0;
      B = 8'h10;
      C = 0;

      #2 `assert (r_c, 1);

      #2 op_sel = 4;
      A = 8'hf0;
      B = 8'h10;
      C = 0;
      #2 `assert (result, 8'hdf);

      #2 C = 1;

      #2 `assert (result, 8'he0);

      #2 op_sel = 5;

      A = 8'hf0;
      B = 8'h00;
      C = 1;

      #2 `assert (result, 8'he1);
      `assert (r_c, 1);

      #2 C = 0;

      #2 `assert (result, 8'he0);

      #2 B = 1;
      C = 0;

      #2 `assert (result, 8'h78);

      #2 A = 8'hf1;
      C = 1;

      #2 `assert (result, 8'hf8);
      `assert (r_c, 1);

      #2 op_sel = 6;

      #500 $finish;
   end

endmodule