slon/tests/test_alu.verilog

module test_alu;
initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, test_alu);
end

`define assert(signal, value) \
if (signal !== value) begin \
   $display("ASSERTION FAILED in %m: signal != value"); \
     $finish; \
       end


    reg [7:0] A;
    reg [7:0] B;
    reg       C;
    reg [2:0] op_sel;

    wire [7:0] result;
    wire       r_z;
    wire       r_n;
    wire       r_c;
    wire       r_v;

`include "parameters.vh"

alu my_alu(
           .A(A),
           .B(B),
           .C(C),
           .sel(op_sel),
           .result(result),
           .r_z(r_z),
           .r_n(r_n),
           .r_c(r_c),
           .r_v(r_v));

initial begin

    // Testing OR
    #10 A = 8'h11;
    B = 8'h22;
    C = 0;
    op_sel = OP_OR;

    #2 `assert (result, 8'h33);

    // Testing AND
    #2 op_sel = OP_AND;

    #2 `assert (result, 8'h00);

    // Testing EOR
    #2 op_sel = OP_EOR;

    #2 `assert (result, 8'h33);

    #2  A = 8'h22;
    B = 8'h22;

    #2 `assert (result, 8'h00);

    // Testing ADC
    // Without carry
    #2 op_sel = OP_ADC;

    #2  A = 8'h22;
    B = 8'h22;
    C = 0;

    #2 `assert (result, 8'h44);

    // With carry
    #2 C = 1;

    #2 `assert (result, 8'h45);

    #2  A = 8'hf0;
    B = 8'h10;
    C = 0;

    #2 `assert (r_c, 1);

    // Test SUB
    #2 op_sel = OP_SUB;
    A = 8'hf0;
    B = 8'h10;
    C = 0;
    #2 `assert (result, 8'hdf);

    #2 C = 1;

    #2 `assert (result, 8'he0);

    // Test ROT
    #2 op_sel = OP_ROT;

    A = 8'hf0;
    B = SHIFT_LEFT;
    C = 1;

    #2 `assert (result, 8'he1);
    `assert (r_c, 1);

    #2 C = 0;

    #2 `assert (result, 8'he0);

    #2 B = SHIFT_RIGHT;
    C = 0;

    #2 `assert (result, 8'h78);

    #2 A = 8'hf1;
    C = 1;

    #2 `assert (result, 8'hf8);
    `assert (r_c, 1);

    // Test SHF
    #2 op_sel = OP_SHF;
    A = 8'hf9;
    B = SHIFT_LEFT;
    #1 `assert (result, 8'hf2);

    B = SHIFT_RIGHT;
    #1 `assert (result, 8'h7c);

    #500 $finish;
end

endmodule