From c643b5d6f6254824d68b174e92d05abbee9233bf Mon Sep 17 00:00:00 2001
From: Denis Tereshkin <denis@kasan.ws>
Date: Sun, 7 Dec 2025 13:37:49 +0700
Subject: [PATCH] Add BIT instruction

---
 src/cpu.verilog | 53 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/src/cpu.verilog b/src/cpu.verilog
index c5d871e..76be8d5 100644
--- a/src/cpu.verilog
+++ b/src/cpu.verilog
@@ -91,6 +91,7 @@ localparam
     logic        pending_rel_branch;
     logic        pending_nz_alu_update;
     logic        pending_c_alu_update;
+    logic        pending_bit_cmd;
     wire         is_arith;
     logic [2:0]  extra_timing;
     reg [3:0]  state_after_delay;
@@ -109,6 +110,7 @@ initial pending_y_read = 0;
 initial pending_rel_branch = 0;
 initial pending_nz_alu_update = 0;
 initial pending_c_alu_update = 0;
+initial pending_bit_cmd = 0;
 initial mem_aux_addr = 0;
 initial instr = 0;
 initial extra_timing = 0;
@@ -290,6 +292,13 @@ always_comb
             alu_op_c = 1'b1;
             alu_op_sel = OP_CMP;
         end
+      else if (decoded_instr == I_BIT)
+        begin
+            alu_op_1 = A;
+            alu_op_2 = mem_data;
+            alu_op_c = 0;
+            alu_op_sel = OP_AND;
+        end
       else
         begin
             alu_op_1 = A;
@@ -400,6 +409,14 @@ always @(posedge clk)
                 end
               pending_c_alu_update <= 0;
 
+              if (pending_bit_cmd)
+                begin
+                    P[P_Z] <= (A & mem_data) == 0;
+                    P[P_V] <= mem_data[6];
+                    P[P_N] <= mem_data[7];
+                    pending_bit_cmd <= 0;
+                end
+
               PC <= PC + 1;
               state <= STATE_EXECUTE;
           end
@@ -624,6 +641,10 @@ always @(posedge clk)
             pending_c_alu_update <= 1;
             pending_nz_alu_update <= 1'b1;
         end
+        else if (decoded_instr == I_BIT)
+          begin
+              pending_bit_cmd <= 1;
+          end
 
         state <= STATE_FETCH;
     end
@@ -722,6 +743,10 @@ always @(posedge clk)
               pending_c_alu_update <= 1;
               pending_nz_alu_update <= 1;
           end
+        else if(decoded_instr == I_BIT)
+          begin
+              pending_bit_cmd <= 1;
+          end
     end
   else if (state == STATE_READ_ADDR_ZP)
     begin
@@ -1466,6 +1491,33 @@ always @(posedge clk)
           assert(Y == f_prev_Y);
       end
 
+always @(posedge clk)
+  if (f_prev_valid && state == STATE_EXECUTE)
+    if (f_prev_instruction == I_BIT)
+      begin
+          cover($past(address_code) == ADDR_MODE_ZP);
+          cover($past(address_code) == ADDR_MODE_ABSOLUTE);
+
+          if ($past(address_code) == ADDR_MODE_ZP)
+            begin
+                assert($past(PC) == $past(f_prev_PC) + 16'd2);
+                assert(f_prev_instr_cycles == 3);
+            end
+          else if ($past(address_code) == ADDR_MODE_ABSOLUTE)
+            begin
+                assert($past(PC) == $past(f_prev_PC) + 16'd3);
+                assert(f_prev_instr_cycles == 4);
+            end
+
+          assert(P[P_Z] == ((A & $past(mem_data)) == 0));
+          assert(P[P_N] == $past(mem_data[7]));
+          assert(P[P_V] == $past(mem_data[6]));
+          assert(A == f_prev_A);
+          assert(S == f_prev_S);
+          assert(X == f_prev_X);
+          assert(Y == f_prev_Y);
+      end
+
 always @(posedge clk)
   if (f_prev_valid && state == STATE_EXECUTE)
     if (f_prev_instruction == I_INC ||
@@ -1776,6 +1828,7 @@ begin
              decoded_instr == I_CMP ||
              decoded_instr == I_CPX ||
              decoded_instr == I_CPY ||
+             decoded_instr == I_BIT ||
              decoded_instr == I_BNE ||
              decoded_instr == I_JMP
 );