diff --git a/src/cpu.verilog b/src/cpu.verilog
index f948a5f..ef2574d 100644
--- a/src/cpu.verilog
+++ b/src/cpu.verilog
@@ -555,6 +555,8 @@ always_comb
 
     logic [7:0] f_prev_instruction;
     logic [4:0] f_prev_addr_code;
+    logic f_prev_instruction_is_branch;
+
 
 initial f_prev_instruction = 0;
 initial f_prev_addr_code = 0;
@@ -600,6 +602,21 @@ always @(posedge clk)
         f_prev_addr_code <= $past(address_code);
     end
 
+always @(*)
+    f_prev_instruction_is_branch <=
+                                   (f_prev_instruction == I_JMP ||
+                                    f_prev_instruction == I_BCC ||
+                                    f_prev_instruction == I_BCS ||
+                                    f_prev_instruction == I_BEQ ||
+                                    f_prev_instruction == I_BMI ||
+                                    f_prev_instruction == I_BNE ||
+                                    f_prev_instruction == I_BPL ||
+                                    f_prev_instruction == I_BVC ||
+                                    f_prev_instruction == I_BVS ||
+                                    f_prev_instruction == I_JSR ||
+                                    f_prev_instruction == I_RTS ||
+                                    f_prev_instruction == I_RTI);
+
 always @(posedge clk)
   if (f2_past_valid && state == STATE_EXECUTE)
     if ($past(decoded_instr) == I_DEX)
@@ -676,8 +693,6 @@ begin
              decoded_instr == I_LDX ||
              decoded_instr == I_LDY ||
              decoded_instr == I_STA ||
-             decoded_instr == I_STX ||
-             decoded_instr == I_STY ||
              decoded_instr == I_AND ||
              decoded_instr == I_EOR ||
              decoded_instr == I_ORA ||
@@ -712,8 +727,6 @@ always @(posedge clk)
           assert(Y == $past(mem_data));
         else if (f_prev_instruction == I_STA)
           assert(A == $past(A));
-        else
-          assume(0);
 
         if (f_prev_instruction == I_STA)
           begin
@@ -800,16 +813,20 @@ always @(posedge clk)
         assert(P[P_D] == $past(P[P_D], 2));
         assert(P[P_I] == $past(P[P_I], 2));
         assert(S == $past(S, 2));
-        if (f_prev_instruction != I_LDX)
+        if (f_prev_instruction != I_LDX &&
+            f_prev_instruction != I_DEX &&
+            f_prev_instruction != I_INX)
           begin
               assert(X == $past(X, 2));
           end
-        if (f_prev_instruction != I_LDY)
+        if (f_prev_instruction != I_LDY &&
+            f_prev_instruction != I_DEY &&
+            f_prev_instruction != I_INY)
           begin
               assert(Y == $past(Y, 2));
           end
 
-        if (f6_past_valid)
+        if (f6_past_valid && !f_prev_instruction_is_branch)
           begin
               if ($past(address_code, 2) == ADDR_MODE_ABSOLUTE)
                 assert($past(PC, 1) == $past(PC, 5) + 16'd3);