diff --git a/src/cpu.verilog b/src/cpu.verilog
index 76be8d5..c307798 100644
--- a/src/cpu.verilog
+++ b/src/cpu.verilog
@@ -864,6 +864,7 @@ always_comb
     logic [7:0] f_prev_instruction;
     logic [4:0] f_prev_addr_code;
     logic f_prev_instruction_is_branch;
+    logic [7:0] f_prev_branch_rel;
     logic [4:0] f_prev_instr_cycles;
     logic [4:0] f_instr_cycles;
 
@@ -881,6 +882,8 @@ initial f_instr_cycles = 0;
 initial f_prev_instruction = 0;
 initial f_prev_addr_code = 0;
 initial f_prev_valid = 0;
+initial f_prev_instruction_is_branch = 0;
+initial f_prev_branch_rel = 0;
 initial f_prev_X = 0;
 initial f_prev_Y = 0;
 initial f_prev_A = 0;
@@ -935,6 +938,9 @@ always @(posedge clk)
         f_instr_cycles <= f_instr_cycles + 1'b1;
     end
 
+always @(posedge clk)
+    if (state == STATE_BRANCH)
+      f_prev_branch_rel <= mem_data;
 
     logic [15:0] f_abs_address;
 
@@ -1794,6 +1800,30 @@ always @(posedge clk)
           assert(Y == f_prev_Y);
       end
 
+always @(posedge clk)
+  if (f_prev_valid && state == STATE_EXECUTE)
+    if (f_prev_instruction == I_BNE)
+      begin
+          assert($past(address_code) == ADDR_MODE_RELATIVE);
+
+          if ($past(P[P_Z]) == 0)
+            begin
+                assert($past(PC) == $past(f_prev_PC) + {{8{f_prev_branch_rel[7]}}, f_prev_branch_rel[7:0]} + 16'd2);
+                assert(f_prev_instr_cycles == 3);
+            end
+          else
+            begin
+                assert($past(PC) == $past(f_prev_PC) + 16'd2);
+                assert(f_prev_instr_cycles == 2);
+            end
+
+          assert(P == f_prev_P);
+          assert(S == f_prev_S);
+          assert(A == f_prev_A);
+          assert(X == f_prev_X);
+          assert(Y == f_prev_Y);
+      end
+
 always @(posedge clk)
     if (f_past_valid)
 begin