diff --git a/src/cpu.verilog b/src/cpu.verilog
index 47c825a..783dd0a 100644
--- a/src/cpu.verilog
+++ b/src/cpu.verilog
@@ -496,6 +496,41 @@ always @(posedge clk)
                     pending_c_alu_update <= 1;
                     state <= STATE_FETCH;
                     end
+              else if (decoded_instr == I_CLC)
+                begin
+                    P[P_C] <= 0;
+                    state <= STATE_FETCH;
+                end
+              else if (decoded_instr == I_SEC)
+                begin
+                    P[P_C] <= 1;
+                    state <= STATE_FETCH;
+                end
+              else if (decoded_instr == I_CLD)
+                begin
+                    P[P_D] <= 0;
+                    state <= STATE_FETCH;
+                end
+              else if (decoded_instr == I_SED)
+                begin
+                    P[P_D] <= 1;
+                    state <= STATE_FETCH;
+                end
+              else if (decoded_instr == I_CLI)
+                begin
+                    P[P_I] <= 0;
+                    state <= STATE_FETCH;
+                end
+              else if (decoded_instr == I_SEI)
+                begin
+                    P[P_I] <= 1;
+                    state <= STATE_FETCH;
+                end
+              else if (decoded_instr == I_CLV)
+                begin
+                    P[P_V] <= 0;
+                    state <= STATE_FETCH;
+                end
           end
         else if (decoded_instr == I_BNE)
           begin
@@ -1469,6 +1504,98 @@ always @(posedge clk)
           assert(Y == f_prev_Y);
       end
 
+always @(posedge clk)
+  if (f_prev_valid && state == STATE_EXECUTE)
+    if (f_prev_instruction == I_CLC ||
+        f_prev_instruction == I_SEC)
+      begin
+          assert($past(address_code) == ADDR_MODE_IMPLIED);
+
+          assert($past(PC) == $past(f_prev_PC) + 16'd1);
+          assert(f_prev_instr_cycles == 2);
+
+          if (f_prev_instruction == I_CLC)
+            begin
+                assert(P[P_C] == 0);
+            end
+          else if (f_prev_instruction == I_SEC)
+            begin
+                assert(P[P_C] == 1);
+            end
+
+          assert(S == f_prev_S);
+          assert(A == f_prev_A);
+          assert(X == f_prev_X);
+          assert(Y == f_prev_Y);
+      end
+
+always @(posedge clk)
+  if (f_prev_valid && state == STATE_EXECUTE)
+    if (f_prev_instruction == I_CLD ||
+        f_prev_instruction == I_SED)
+      begin
+          assert($past(address_code) == ADDR_MODE_IMPLIED);
+
+          assert($past(PC) == $past(f_prev_PC) + 16'd1);
+          assert(f_prev_instr_cycles == 2);
+
+          if (f_prev_instruction == I_CLD)
+            begin
+                assert(P[P_D] == 0);
+            end
+          else if (f_prev_instruction == I_SED)
+            begin
+                assert(P[P_D] == 1);
+            end
+
+          assert(S == f_prev_S);
+          assert(A == f_prev_A);
+          assert(X == f_prev_X);
+          assert(Y == f_prev_Y);
+      end
+
+always @(posedge clk)
+  if (f_prev_valid && state == STATE_EXECUTE)
+    if (f_prev_instruction == I_CLI ||
+        f_prev_instruction == I_SEI)
+      begin
+          assert($past(address_code) == ADDR_MODE_IMPLIED);
+
+          assert($past(PC) == $past(f_prev_PC) + 16'd1);
+          assert(f_prev_instr_cycles == 2);
+
+          if (f_prev_instruction == I_CLI)
+            begin
+                assert(P[P_I] == 0);
+            end
+          else if (f_prev_instruction == I_SEI)
+            begin
+                assert(P[P_I] == 1);
+            end
+
+          assert(S == f_prev_S);
+          assert(A == f_prev_A);
+          assert(X == f_prev_X);
+          assert(Y == f_prev_Y);
+      end
+
+always @(posedge clk)
+  if (f_prev_valid && state == STATE_EXECUTE)
+    if (f_prev_instruction == I_CLV)
+      begin
+          assert($past(address_code) == ADDR_MODE_IMPLIED);
+
+          assert($past(PC) == $past(f_prev_PC) + 16'd1);
+          assert(f_prev_instr_cycles == 2);
+
+          assert(P[P_V] == 0);
+
+          assert(S == f_prev_S);
+          assert(A == f_prev_A);
+          assert(X == f_prev_X);
+          assert(Y == f_prev_Y);
+      end
+
 always @(posedge clk)
     if (f_past_valid)
 begin
@@ -1493,6 +1620,13 @@ begin
              decoded_instr == I_LSR ||
              decoded_instr == I_ROR ||
              decoded_instr == I_ROL ||
+             decoded_instr == I_CLC ||
+             decoded_instr == I_SEC ||
+             decoded_instr == I_CLD ||
+             decoded_instr == I_SED ||
+             decoded_instr == I_CLI ||
+             decoded_instr == I_SEI ||
+             decoded_instr == I_CLV ||
              decoded_instr == I_BNE ||
              decoded_instr == I_JMP
 );